Espressif Systems /ESP32-P4 /H264 /INT_ST

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Interpret as INT_ST

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DB_TMP_READY_INT_ST)DB_TMP_READY_INT_ST 0 (REC_READY_INT_ST)REC_READY_INT_ST 0 (FRAME_DONE_INT_ST)FRAME_DONE_INT_ST 0 (DMA_MOVE_2MB_LINE_DONE_INT_ST)DMA_MOVE_2MB_LINE_DONE_INT_ST

Description

Interrupt masked status register

Fields

DB_TMP_READY_INT_ST

The masked interrupt status of H264_DB_TMP_READY_INT. Valid only when the H264_DB_TMP_READY_INT_ENA is set to 1.

REC_READY_INT_ST

The masked interrupt status of H264_REC_READY_INT. Valid only when the H264_REC_READY_INT_ENA is set to 1.

FRAME_DONE_INT_ST

The masked interrupt status of H264_FRAME_DONE_INT. Valid only when the H264_FRAME_DONE_INT_ENA is set to 1.

DMA_MOVE_2MB_LINE_DONE_INT_ST

Masked status bit: The masked interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Valid only when the H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA is set to 1.

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